News

Korean National Science & Technology Commission A delegation of the Korean National Science & Technology Commission (NSTC) Delegation led by Dr. Cha-Dong Kim visited us on 7 December.
For more information about NSTC visit the website.

Society for the Advancement of Material and Process Engineering During the Society for the Advancement of Material and Process Engineering (SAMPE) Benelex Student meeting, Niels De Greef is selected for the best presentation award together with a student from UCL and is nominated for the JEC award competition, which will be held in conjunction with the SAMPE Europe Student Meeting in Paris, March 2012. Congratulations!

Niels De Greef will receive a KU Leuven policy mandate for one year for his excellent performance. Well done!

Recent Highlights

Correlation between strain and the metal–insulator transition in epitaxial V2O3 thin films grown by Molecular Beam EpitaxyCorrelation between strain and the metal–insulator transition in epitaxial V2O3 thin films grown by Molecular Beam Epitaxy by L. Dillemans et al.,


Deposition and characterization of MgO/Si gate stacksDeposition and characterization of MgO/Si gate stacks grown by molecular beam epitaxy by Chen-Yi Su et al.,


Thermally induced phase separation in PaMSAN/PMMA blends in presence of functionalized multiwall carbon nanotubes: Rheology, morphology and electrical conductivity by Ceren Özdilek et al.,


Striking influence of the catalyst support and its acid-base properties: New insight into the growth mechanism of carbon nanotubes by Arnaud Magrez et al.,


Fabrication of homogeneous titania/MWNT composite materials by Barbara Korbély et al.,


Research

Tailored oxide – semiconductor interfaces

Oxide-semiconductor interfaces are at the core of any metal-oxide-semiconductor field effect transistor technology (MOSFET). The Si – SiO2 interface is currently the only such interface that shows a low ‘electrical’ defect density (1010/cm2). There are several reasons that make this interface unique, such as the gradient in Si valence moving gradually from Si0 via Si+1 – Si+2 – Si+3 to Si+4 in SiO2 as well as the possibility to passivate the ‘electrically active’ defects using hydrogen anneals. Nevertheless, this interface is not perfect, as indicated by the decrease of the electron mobility in the surface channel to 300 cm2/Vs from a bulk value of 1500 cm2/Vs. Any improvement in mobility would have an important and direct impact on the transistor performance [1].

In order to increase this performance further, there is a strong drive to replace the Si – SiO2 system by using a different oxide, a different semiconductor or their combination. The oxides being considered have a higher dielectric constant (10 – 30) while the interesting semiconductors are those which have a high mobility such as Ge[2] (particularly for p-MOSFET) and GaAs/InGaAs [3] (particularly for n-MOSFET). At this stage, there is no interface configuration for these new systems that comes close in electrical quality to that of the Si – SiO2 couple.

In this research project, two novel approaches to the creation of the semiconductor – oxide interfaces are proposed, whereby the Si – SiO2 system will function as a model system. In particular, the main goal is to create interfaces with ‘large” valence gradients over about 0.6 – 1.0 nm. This will be achieved using both novel growth methods as well as annealing methods followed with in-situ and ex-situ characterization techniques.

This research topic is related to the activities in the EU FP7 projects DualLogic ( http://www.ims.demokritos.gr/DUALLOGIC/) in collaboration with NCSR-Demokritos, IMEC, Aixtron, IBM, LETI, ST Microelectronics, NXP and U. Glasgow.

[1] For a recent review, J.-P. Locquet et al., J. Appl. Phys. 100, 051610 (2006).
[2] J. W. Seo et al., Appl. Phys. Lett. 87, 221906 (2005).
[3] S. Koester et al., Appl. Phys. Lett. 89, 042104 (2006).


D. Fischer et al., Appl. Phys. Lett., 88, 012101 (2006)


Enhancement-mode buried-channel In0.7Ga0.3As/In0.52Al0.48As MOSFETs with high-kappa gate dielectrics
Y.N. Sun, E. Kiewra, S. Koester, N. Ruiz, A. Callegari, K. Fogel, D. Sadana, J. Fompeyrine, D. Webb, J.P. Locquet, M. Sousa, R. Germann, K. Shiu and S. Forrest,
IEEE Electron Device Letters 28, pp. 473-475 (2007).

Evidence of electron and hole inversion in GaAs metal-oxide-semiconductor capacitors with HfO2 gate dielectrics and alpha-Si/SiO2 interlayers
S. Koester, E. Kiewra, Y.N. Sun, D. Neumayer, J.A. Ott, M. Copel, D. Sadana, D. Webb, J. Fompeyrine, J.P. Locquet, C. Marchiori, M. Sousa and R. Germann,
Applied Physics Letters 89, 042104 (2006).

Band-edge high-performance high-k/metal gate n-MOSFETs using cap layers containing Group IIA and IIIB elements with gate-first processing for 45 nm and beyond
V. Narayanan, V.K. Paruchuri, N.A. Bojarczuk, B.P. Linder, B. Doris, Y.H. Kim, S. Zafar, J. Stathis, S. Brown, J. Arnold, M. Copel, M. Steen, E. Cartier, A. Callegari, P. Jamison, J.P. Locquet, D.L. Lacey, Y. Wang, P.E. Batson, P. Ronsheim, R. Jammy, M.P. Chudzik, M. Ieong, S. Guha, G. Shahidi and T.C. Chen,
2006 Symposium on VLSI Technology (IEEE Cat. No. 06CH37743C) pp. 2 (2006).